Erlang on RISC-V

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Erlang on RISC-V

Mikael Karlsson-7
Hi,

has anyone looked at having the Erlang compiler support RISC-V,
https://riscv.org/ ,  ISA?
Seems that RISC-V is catching momentum and many other compilers like
Rust, Go etc. are being ported.

Regards
Mikael Karlsson
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Re: Erlang on RISC-V

Matthias Lang
On 19. February 2018, Mikael Karlsson wrote:

> has anyone looked at having the Erlang compiler support RISC-V,

I haven't.

What do you mean by "the Erlang compiler"?

The regular Erlang compiler, i.e. the one that generates .beam files,
generates .beam files which don't care what CPU you want to run on.

HiPE is a different story, but you didn't mention HiPE.

Getting the VM to run is another task, though once people have linux
and a toolchain running (I see that there's an active debian effort,
for instance), I would expect that to be the same level of difficulty
as compiling on, say, MIPS linux for the first time---i.e. maybe it'll
just work, maybe you have to do a bit of autotools fiddling.

---

The mention of RISC-V just made me think, "I haven't heard anything
about Tilera for a while". I think it's been a few years since anyone
here said anything about it on the mailing list. Anyone know if it's
still alive?

(Wikipedia says they were acquired by EZchip, the Tilera website says
EZchip was acquired by Mellanox. Mellanox still have them listed as a
product, but is this thriving or a zombie?)

Matt
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Re: Erlang on RISC-V

Mikael Pettersson-5
On Tue, Feb 20, 2018 at 11:49 AM, Matthias Lang <[hidden email]> wrote:

> On 19. February 2018, Mikael Karlsson wrote:
>
>> has anyone looked at having the Erlang compiler support RISC-V,
>
> I haven't.
>
> What do you mean by "the Erlang compiler"?
>
> The regular Erlang compiler, i.e. the one that generates .beam files,
> generates .beam files which don't care what CPU you want to run on.
>
> HiPE is a different story, but you didn't mention HiPE.

RISC-V support in HiPE should be straight-forward, but no-one is
working on that AFAIK.
It's not clear there is any need, since the BEAM should work as-is.

There is also that HiPE/LLVM thing which might be able to support RISC-V
with less effort.

> Getting the VM to run is another task, though once people have linux
> and a toolchain running (I see that there's an active debian effort,
> for instance), I would expect that to be the same level of difficulty
> as compiling on, say, MIPS linux for the first time---i.e. maybe it'll
> just work, maybe you have to do a bit of autotools fiddling.

RISC-V has full GNU/Linux support with latest GCC, binutils, GLIBC,
and Linux kernel, and I know both Debian and Fedora have started ports.
But you don't need to wait for a full distro port, all you need is a
cross-compiler
and busybox or sth and you're done.

> The mention of RISC-V just made me think, "I haven't heard anything
> about Tilera for a while". I think it's been a few years since anyone
> here said anything about it on the mailing list. Anyone know if it's
> still alive?

Tilera is dropping their Tile processors and migrating to some other core
(I don't know which one, but probably ARM or MIPS.)  See e.g. their recent
announcements to drop the older TilePro from Linux and glibc, keeping only
Tile-Gx due to some customers still using it.
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Re: Erlang on RISC-V

Mikael Karlsson-7
Thanks for the info Mikael and Matthias.

>> What do you mean by "the Erlang compiler"?

I guess I meant the VM, I haven't posted to the posted to the list for
a while and so lost some of my stringency.
Thanks for setting me back on track. :-).

>There is also that HiPE/LLVM thing which might be able to support RISC-V with less effort.

OK, so maybe some involvement of the compiler anyway.
Seems there is a RISC-V backend for LLVM in the works.
https://github.com/lowRISC/riscv-llvm

Mikael K
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Re: Erlang on RISC-V

Mathieu Kerjouan
Hi,

I've you take a look on Parallella[1] board based on RISC-V ISA? A paper[2] on porting Erlang on this board was made in 2016. Source code is available on github[3].

[1] https://www.parallella.org/
[2] Erlang on Adapteva's Parallella http://uu.diva-portal.org/smash/get/diva2:1045465/FULLTEXT01.pdf
[3] https://github.com/parallella/otp
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Re: Erlang on RISC-V

Mikael Pettersson-5
On Sat, Feb 24, 2018 at 2:37 PM, Mathieu Kerjouan
<[hidden email]> wrote:
> Hi,
>
> I've you take a look on Parallella[1] board based on RISC-V ISA? A paper[2] on porting Erlang on this board was made in 2016. Source code is available on github[3].
>
> [1] https://www.parallella.org/
> [2] Erlang on Adapteva's Parallella http://uu.diva-portal.org/smash/get/diva2:1045465/FULLTEXT01.pdf
> [3] https://github.com/parallella/otp

That board is not based on RISC-V, instead its processor is an
ARM/Epiphany combination.  The Epiphany is a low-power, high
core-count, number crunching co-processor for embedded computing.
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Re: Erlang on RISC-V

Mikael Karlsson-7
In reply to this post by Mikael Karlsson-7
Hi again,
just an update on RISC-V and Erlang.
It seems there is already a fedora project for RISC-V:
https://fedoraproject.org/wiki/Architectures/RISC-V

So following instructions from the wiki, downloading diskimage and
getting a proper QEMU going one can install erlang after booting:

[root@stage4 ~]# dnf install erlang
[root@stage4 ~]# uname -a
Linux stage4.fedoraproject.org 4.15.0-00044-g2b0aa1de45f6 #24 SMP Sat
Apr 21 11:50:47 UTC 2018 riscv64 riscv64 riscv64 GNU/Linux
[root@stage4 ~]# erl
Erlang/OTP 20 [erts-9.3] [source] [64-bit] [smp:4:4] [ds:4:4:10]
[async-threads:10] [kernel-poll:false]

Eshell V9.3  (abort with ^G)
1> 11.0 / 7.
1.5714285714285714
2>

"Right out of the box". Best would of course be to burn your own FPGA,
cross-compile complete nerves-project and install....


2018-02-20 15:07 GMT+01:00 Mikael Karlsson <[hidden email]>:

> Thanks for the info Mikael and Matthias.
>
>>> What do you mean by "the Erlang compiler"?
>
> I guess I meant the VM, I haven't posted to the posted to the list for
> a while and so lost some of my stringency.
> Thanks for setting me back on track. :-).
>
>>There is also that HiPE/LLVM thing which might be able to support RISC-V with less effort.
>
> OK, so maybe some involvement of the compiler anyway.
> Seems there is a RISC-V backend for LLVM in the works.
> https://github.com/lowRISC/riscv-llvm
>
> Mikael K
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Re: Erlang on RISC-V

Mikael Karlsson-7
In reply to this post by Mikael Pettersson-5
2018-02-20 14:45 GMT+01:00 Mikael Pettersson <[hidden email]>:
On Tue, Feb 20, 2018 at 11:49 AM, Matthias Lang <[hidden email]> wrote:
> On 19. February 2018, Mikael Karlsson wrote:
>
>> has anyone looked at having the Erlang compiler support RISC-V,
>
> I haven't.
>
> What do you mean by "the Erlang compiler"?
>
> The regular Erlang compiler, i.e. the one that generates .beam files,
> generates .beam files which don't care what CPU you want to run on.
>
> HiPE is a different story, but you didn't mention HiPE.

RISC-V support in HiPE should be straight-forward, but no-one is
working on that AFAIK.
It's not clear there is any need, since the BEAM should work as-is.

There is also that HiPE/LLVM thing which might be able to support RISC-V
with less effort.

> Getting the VM to run is another task, though once people have linux
> and a toolchain running (I see that there's an active debian effort,
> for instance), I would expect that to be the same level of difficulty
> as compiling on, say, MIPS linux for the first time---i.e. maybe it'll
> just work, maybe you have to do a bit of autotools fiddling.

RISC-V has full GNU/Linux support with latest GCC, binutils, GLIBC,
and Linux kernel, and I know both Debian and Fedora have started ports.
But you don't need to wait for a full distro port, all you need is a
cross-compiler
and busybox or sth and you're done.

> The mention of RISC-V just made me think, "I haven't heard anything
> about Tilera for a while". I think it's been a few years since anyone
> here said anything about it on the mailing list. Anyone know if it's
> still alive?

Tilera is dropping their Tile processors and migrating to some other core
(I don't know which one, but probably ARM or MIPS.)  See e.g. their recent
announcements to drop the older TilePro from Linux and glibc, keeping only
Tile-Gx due to some customers still using it.

Hi again Mikael,

>It's not clear there is any need, since the BEAM should work as-is.

Yes, the Fedora port you pointed out has already an Erlang port.

However the RISC-V is a register machine (as the Erlang VM) with 32 integer registers so I wonder it there are any optimizations that may be done.
I can see in the beam_emu.c a can see for other architectures sections like:
/*
 * On certain platforms, make sure that the main variables really are placed
 * in registers.
 */
..
#elif defined(__GNUC__) && defined(__amd64__) && !defined(DEBUG)
#  define REG_xregs asm("%r12")
#  define REG_htop
#  define REG_stop asm("%r13")
#  define REG_I asm("%rbx")
#  define REG_fcalls asm("%r14")
#else
..
The RISC-V assembly programmer's handbook lists registers as (chapter 20 in the spec):
Register ABI Name Description Saver
x0 zero Hard-wired zero |
x1 ra Return address Caller
x2 sp Stack pointer Callee
x3 gp Global pointer |
x4 tp Thread pointer |
x5 t0 Temporary/alternate link register Caller
x6-7 t1-2 Temporaries Caller
x8 s0/fp Saved register/frame pointer Callee
x9 s1 Saved register Callee
x10-11 a0-1 Function arguments/return values Caller
x12-17 a2-7 Function arguments Caller
x18-27 s2-11 Saved registers Callee
x28-31 t3-6 Temporaries Caller

So I guess some similar "reservations" can be made for RISC-V as for amd64, but I am not sure how to map them here.

Best Regards
Mikael K



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Re: Erlang on RISC-V

Mikael Pettersson-5
On Fri, May 11, 2018 at 3:15 PM, Mikael Karlsson <[hidden email]> wrote:

>>It's not clear there is any need, since the BEAM should work as-is.
>
> Yes, the Fedora port you pointed out has already an Erlang port.
>
> However the RISC-V is a register machine (as the Erlang VM) with 32 integer
> registers so I wonder it there are any optimizations that may be done.
> I can see in the beam_emu.c a can see for other architectures sections like:
> /*
>  * On certain platforms, make sure that the main variables really are placed
>  * in registers.
>  */
> ..
> #elif defined(__GNUC__) && defined(__amd64__) && !defined(DEBUG)
> #  define REG_xregs asm("%r12")
> #  define REG_htop
> #  define REG_stop asm("%r13")
> #  define REG_I asm("%rbx")
> #  define REG_fcalls asm("%r14")
> #else
> ..
> The RISC-V assembly programmer's handbook lists registers as (chapter 20 in
> the spec):
> Register ABI Name Description Saver
> x0 zero Hard-wired zero |
> x1 ra Return address Caller
> x2 sp Stack pointer Callee
> x3 gp Global pointer |
> x4 tp Thread pointer |
> x5 t0 Temporary/alternate link register Caller
> x6-7 t1-2 Temporaries Caller
> x8 s0/fp Saved register/frame pointer Callee
> x9 s1 Saved register Callee
> x10-11 a0-1 Function arguments/return values Caller
> x12-17 a2-7 Function arguments Caller
> x18-27 s2-11 Saved registers Callee
> x28-31 t3-6 Temporaries Caller
>
> So I guess some similar "reservations" can be made for RISC-V as for amd64,
> but I am not sure how to map them here.

This can be done of course.  The code reserves callee-save registers
for important
BEAM VM variables on SPARC and AMD64, so you should identify 5 callee-save
registers in the RISC-V ABI and bind them in a similar way.  Your list
is a bit unclear,
but I guess the s0-s11 registers are callee-save; pick say the last 5.

It's probably not worth trying to bind even more BEAM VM variables to
registers, as
that means more work in transitions in to and out of process_main().

You'll want to run the estone SUITE to see how much of a difference
register variables
make on RISC-V.

/Mikael
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Re: Erlang on RISC-V

Mikael Karlsson-7
2018-05-11 18:52 GMT+02:00 Mikael Pettersson <[hidden email]>:

>
> On Fri, May 11, 2018 at 3:15 PM, Mikael Karlsson <[hidden email]> wrote:
> >>It's not clear there is any need, since the BEAM should work as-is.
> >
> > Yes, the Fedora port you pointed out has already an Erlang port.
> >
> > However the RISC-V is a register machine (as the Erlang VM) with 32 integer
> > registers so I wonder it there are any optimizations that may be done.
> ...
>
> > So I guess some similar "reservations" can be made for RISC-V as for amd64,
> > but I am not sure how to map them here.
>
> This can be done of course.  The code reserves callee-save registers for important
> BEAM VM variables on SPARC and AMD64, so you should identify 5 callee-save
> registers in the RISC-V ABI and bind them in a similar way.  Your list is a bit unclear,
> but I guess the s0-s11 registers are callee-save; pick say the last 5.
>
> It's probably not worth trying to bind even more BEAM VM variables to
> registers, as that means more work in transitions in to and out of process_main().
>
> You'll want to run the estone SUITE to see how much of a difference
> register variables make on RISC-V.

Great,

many thanks for the info.

Also for anyone interested the last RISC-V workshop just finished in Barcelona,
https://riscv.org/2018/04/risc-v-workshop-in-barcelona-agenda/

/Mikael K
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